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ADT7473
Table 86. REGISTER 0X75 ? INTERRUPT MASK REGISTER 2 (POWER-ON DEFAULT <7:0> = 0X00)
Bit No.
<1>
<2>
<3>
<4>
<5>
<6>
<7>
Mnemonic
OVT
FAN1
FAN2
FAN3
F4P
D1
D2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
OVT = 1, masks SMBALERT for overtemperature THERM conditions.
FAN1 = 1, masks SMBALERT for a Fan 1 fault.
FAN2 = 1, masks SMBALERT for a Fan 2 fault.
FAN3 = 1, masks SMBALERT for a Fan 3 fault.
F4P = 1, masks SMBALERT for a Fan 4 fault. If the TACH4 pin is being used as the THERM
input, this bit masks SMBALERT for a THERM timer event.
D1 = 1, masks SMBALERT for a diode open or short on a Remote 1 channel.
D2 = 1, masks SMBALERT for a diode open or short on a Remote 2 channel.
Table 87. REGISTER 0X76 ? EXTENDED RESOLUTION REGISTER 1 (POWER-ON DEFAULT = 0X00) (Note 1)
Bit No.
<3:2>
<5:4>
Mnemonic
V CCP
V CC
R/W
Read-only
Read-only
Description
V CCP LSBs. Holds the 2 LSBs of the 10-bit V CCP measurement.
V CC LSBs. Holds the 2 LSBs of the 10-bit V CC measurement.
1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 88. REGISTER 0X77 ? EXTENDED RESOLUTION REGISTER 2 (POWER-ON DEFAULT = 0X00) (Note 1)
Bit No.
<3:2>
<5:4>
<7:6>
Mnemonic
TDM1
LTMP
TDM2
R/W
Read-only
Read-only
Read-only
Description
Remote 1 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1 temperature
measurement.
Local temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement.
Remote 2 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2 temperature
measurement.
1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 89. REGISTER 0X78 ? CONFIGURATION REGISTER 3 (POWER-ON DEFAULT = 0X00)
Bit No.
<0>
<1>
<2>
<3>
<4>
<5>
<6>
<7>
Mnemonic
ALERT
Enable
THERM
BOOST
FAST
DC1
DC2
DC3
DC4
R/W (Note 1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
ALERT = 0 (default), ADT7473 Pin 5 is configured as PWM2.
ALERT = 1, Pin 5 for ADT7473 (PWM2/SMBALERT) is configured as an SMBALERT
interrupt output to indicate out-of-limit error conditions.
ALERT = 0 (default), ADT7473 ? 1 P in 5 is configure d as. THERM_LATCH.
ALERT = 1, Pin 5 for ADT7473 ? 1 (THERM_LATCH/PWM2) is configured as PWM2.
THERM Enable = 1 enables THERM functionality on Pin 9. Also determined by Bit 0 and
Bit 1 (PIN9FUNC) of Configuration Register 4. Direction is controlled by Bit 5, Bit 6, and Bit 7
of Configuration Register 5 (0x7C). When THERM is asserted, if the fans are running and the
boost bit is set, the fans run at full speed. THERM can also be programmed so that a timer
monitors the duration THERM has been asserted.
When THERM is an input and BOOST = 1, assertion of THERM causes all fans to run at the
maximum programmed duty cycle for fail-safe cooling.
FAST = 1, enables fast TACH measurements on all channels. This increases the TACH
measurement rate from once per second to once every 250 ms (4x).
DC1 = 1, enables TACH measurements to be continuously made on TACH1. Fans must be
driven by dc. Setting this bit prevents pulse stretching because it is not required for dc-driven
motors.
DC2 = 1, enables TACH measurements to be continuously made on TACH2. Fans must be
driven by dc. Setting this bit prevents pulse stretching because it is not required for dc-driven
motors.
DC3 = 1, enables TACH measurements to be continuously made on TACH3. Fans must be
driven by dc. Setting this bit prevents pulse stretching because it is not required for dc-driven
motors.
DC4 = 1, enables TACH measurements to be continuously made on TACH4. Fans must be
driven by dc. Setting this bit prevents pulse stretching because it is not required for dc-driven
motors.
1. This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any further attempts to write to this register have no
effect.
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